Field of the Disclosure
The present disclosure relates to a liquid crystal display (LCD) device, and more particularly, to a narrow bezel-type LCD capable of minimizing the width of a non-display region to embody borderless products.
Discussion of the Related Art
In general, a liquid crystal display (LCD) device may operate based on optical anisotropy of LCs.
Specifically, in the LCD device, when a voltage is applied, molecular arrangement of LCs may be changed according to the intensity of an electric field, and light may be controlled according to the molecular arrangement of the LCs to create images. The LCD device may include an upper substrate having a common electrode, a lower substrate having pixel electrodes, and an LC layer filled between the upper and lower substrates.
An LCD will now be described in further detail with reference to FIGS. 1 and 2.
FIG. 1 is a schematic plan view of the related art LCD device, and FIG. 2 is a schematic cross-sectional view of the related art LCD device.
Referring to FIGS. 1 and 2, a typical LCD 1 may include a color filter substrate 30 having a color filter layer 35, an array substrate 10 having thin film transistors (TFTs), gate lines (not shown), data lines (not shown), and pixel electrodes 15, and an LC layer 40 interposed between the color filter substrate 30 and the array substrate 10.
A plurality of gate pad electrodes (not shown) and a plurality of data pad electrodes (not shown) may be respectively formed on non-display regions NA1 and NA4 disposed on upper and left sides of the array substrate 10, and connected to an external driver circuit. Gate link lines (not shown) and data link lines (not shown) may be respectively formed on the upper and left sides of the array substrate 10, and connected to the plurality of gate pad electrodes and the plurality of data pad electrodes.
In addition, a plurality of gate lines (not shown) and a plurality of data lines (not shown) may be disposed across each other in a display region DA of the array substrate 10 to define a plurality of pixel regions (not shown). The plurality of gate lines may be respectively connected to the gate pad electrodes through the gate link lines, and extend in a widthwise direction. The data lines may be respectively connected to the data pad electrodes through the data link lines, and extend in a lengthwise direction.
Furthermore, the TFTs may be respectively formed near intersections between the gate and data lines, and a pixel electrode 15 may be formed in each of the pixel regions and connected to a drain electrode (not shown) of the corresponding TFT.
The color filter substrate 30 may be formed opposite the array substrate 10 having the above-described structure. The color filter layer 35 and black matrices (not shown) may be formed on the color filter substrate 30, and a common electrode may be formed on the entire surface of the color filter substrate 30. The color filter layer 35 may include red(R), green(G), and blue(B) color filter patterns (not shown) sequentially and repetitively provided to correspond to the respective pixel regions. The black matrices may be formed between the respective color patterns and surround the gate lines and data lines of the array substrate 10, and correspond to non-display regions NA1, NA2, NA3, and NA4 configured to surround an outer portion of the display region DA.
In addition, the LC layer 40 may be interposed between the array substrate 10 and the color filter substrate 30. A seal pattern 42 corresponding to edges of the two substrates 10 and 30 may be formed in the non-display regions NA1, NA2, NA3, and NA4 to form an LC panel 2.
A backlight unit (BLU) used as a light source may be provided on an outer side surface of the array substrate 10 of the LC panel 2 having the above-described construction. A driver (not shown) configured to drive the LC panel 2 may be disposed at an outer portion of the LC panel 2 to complete the LCD device 1.
In general, the driver may be embodied on a printed circuit board (PCB) 50, which may be divided into a gate PCB (not shown) connected to the gate lines of the LC panel 2, and a data PCB 50 connected to the data lines.
Furthermore, the PCB 50 may be mounted on the non-display regions NA1, NA2, NA3, and NA4 disposed outside the display region DA of the LC panel 2.
That is, the PCB 50 may be in contact with the data pad electrodes connected to the data lines through a tape carrier package (TCP) technique or a flexible printed circuit boards (FPCs) 61 and 62 in one side of the array substrate 10.
In this case, instead of the gate PCB, a plurality of gate FPCs 61 including driver IC chips 71 may be mounted on the fourth non-display region NA4 including the gate pad electrodes, and electrically connected to the data PCB 50 adhered to the first non-display region NA1 including the data pad electrodes via a plurality of data FPCs 62 in the array substrate 10.
The LCD device 1 having the above-described construction has briskly been applied to various electronic devices, such as televisions (TVs), monitors, laptop computers, cellular phones, and personal digital assistants (PDAs).
In the latest display devices, maximizing the size of the display region DA, and minimizing the sizes of the non-display devices NA1, NA2, NA3, and NA4 have been required.
However, as described above, in the conventional LCD device 1 in which the PCBs 50 are mounted on the fourth non-display device NA4 having the gate pad electrodes, and the first non-display region NA1 having the data pad electrodes by interposing the FPCs 61 and 62, the gate and data PCBs 50 may be mounted on at least two side surfaces of the LCD device 1 by interposing the FPCs 61 and 62. Alternatively, the data PCB 50 may be mounted on the first non-display region NA1 having the data pad electrodes by interposing the FPC 62 therebetween, while the driver IC chips 71 configured to process gate signals may be mounted on the fourth non-display region NA4 having the gate pad electrodes.
That is, the FPCs 61 and 62 to which the PCB 50 or the driver IC chips 71 are adhered may be mounted on the non-display regions NA1, NA2, NA3, and NA4 of the array substrate 10. After the FPCs 61 and 62 are mounted on the array substrate 10, the FPCs 61 and 62 may be bent and disposed on a rear surface of the array substrate 10 during modularization with a backlight unit BLU.
In the conventional LCD 1 having the above-described construction, the FPCs 61 and 62 may be bent along end tips of side surfaces of the array substrate 10. Finally, a width w1 of the non-display regions NA of the LCD device 1 may expand by as much as a thickness d1 of each of the FPCs 61 and 62 and a distance d2 between each of the FPCs 61 and 62 and the end of the side surface of the array substrate 10, so it is difficult to provide borderless products having narrow bezels.